B. Prévitali

Impact of SOI, Si<inf>1-x</inf>Ge<inf>x</inf>OI and GeOI substrates on CMOS compatible Tunnel FET performance

F. Mayer, C. Le Royer, J.-F. Damlencourt et al. · 2008 · 237 citations

Semiconductor Technology, Electrical Engineering, Engineering +12

Advances, challenges and opportunities in 3D CMOS sequential integration

P. Batude, M. Vinet, B. Prévitali et al. · 2011 · 148 citations · Full text

Materials Science, 3D Ic Architecture, Wafer Scale Processing +15

Performance and design considerations for gate-all-around stacked-NanoWires FETs

Sylvain Barraud, V. Lapras, B. Prévitali et al. · 2017 · 147 citations · Full text

Electrical Engineering, Gate-all-around Stacked-nanowires Fets, Engineering +10

3DVLSI with CoolCube process: An alternative path to scaling

P. Batude, C. Fenouillet-Béranger, L. Pasini et al. · 2015 · 134 citations

Engineering, Vlsi Design, Computer Architecture +23

Multiple gate devices: advantages and challenges

T. Poiroux, M. Vinet, O. Faynot et al. · Microelectronic Engineering · 2005 · 130 citations

Electrical Engineering, Engineering, Device Integration +4