C. Le Royer

Impact of SOI, Si<inf>1-x</inf>Ge<inf>x</inf>OI and GeOI substrates on CMOS compatible Tunnel FET performance

F. Mayer, C. Le Royer, J.-F. Damlencourt et al. · 2008 · 237 citations

Semiconductor Technology, Electrical Engineering, Engineering +12

Advances, challenges and opportunities in 3D CMOS sequential integration

P. Batude, M. Vinet, B. Prévitali et al. · 2011 · 148 citations · Full text

Materials Science, 3D Ic Architecture, Wafer Scale Processing +15

TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model

Arnab Biswas, Surya Shankar Dan, C. Le Royer et al. · Microelectronic Engineering · 2012 · 140 citations · Full text

Device Modeling, Electrical Engineering, Engineering +10

Tunneling FETs on SOI: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling

Jing Wan, C. Le Royer, A. Zaslavsky et al. · Solid-State Electronics · 2011 · 124 citations

Electrical Engineering, Engineering, Tunneling Microscopy +9

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

Louis Hutin, C. Le Royer, J.-F. Damlencourt et al. · IEEE Electron Device Letters · 2010 · 122 citations

Engineering, Integrated Circuits, Geoi Pmosfets +17