Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

Abstract

We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -variability performances are obtained (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</sub> =1.45mV.μm). This leads to 6T-SRAM cells with good characteristics down to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SNM</sub> <;SNM/6) down to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.7V. We also demonstrate ultra-low leakage (<;0.5pA/μm) on UT2B devices at L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).