Y. Morand

Bonded planar double-metal-gate NMOS transistors down to 10 nm

M. Vinet, T. Poiroux, J. Widiez et al. · IEEE Electron Device Letters · 2005 · 129 citations

Engineering, Electrical Engineering, Materials Science +17

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

Sylvain Barraud, V. Lapras, Marie-Pierre Samson et al. · 2016 · 110 citations · Full text

Engineering, Electrical Engineering, Materials Science +17

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

F. Andrieu, O. Weber, J. Mazurier et al. · 2010 · 103 citations

Engineering, Computer Engineering, Electrical Engineering +17

High quality Germanium-On-Insulator wafers with excellent hole mobility

Quang Trung Nguyen, J.F. Damlencourt, Benjamin Vincent et al. · Solid-State Electronics · 2007 · 65 citations

Engineering, Materials Engineering, Materials Science +10

50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process

S. Monfray, T. Skotnicki, Y. Morand et al. · 2003 · 58 citations

Engineering, Computer Engineering, Electrical Engineering +15