Source-drain Engineering
Source-Drain Engineering is a device design methodology in Metal-Oxide-Semiconductor Field-Effect Transistors that involves the intentional modification of the source and drain regions' doping profiles, materials, or geometries to mitigate short-channel effects and enhance carrier transport, thereby improving transistor performance and scalability.
368
Publications
12.4K
Citations
1.7K
Authors
284
Institutions
Publications per year
2017–2026
59
368
Eng-Huat Toh, Grace Huiqi Wang, Ganesh S. Samudra et al. · Journal of Applied Physics · 2008 · 196 citations
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National University of Singapore
Singapore, Singapore
18 h-index
125 publications
3.4K citations
IMEC
Leuven, Belgium
14 h-index
184 publications
5.5K citations
Toshiba (Japan)
Tokyo, Japan
13 h-index
121 publications
5.1K citations
Institute of Microelectronics
Singapore, Singapore
12 h-index
44 publications
1.2K citations
IBM (United States)
Armonk, United States
12 h-index
96 publications
5.5K citations
Institute of Microelectronics
Beijing, China
12 h-index
93 publications
2.3K citations
KU Leuven
Leuven, Belgium
12 h-index
37 publications
884 citations
The University of Tokyo
Tokyo, Japan
12 h-index
44 publications
1.8K citations
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33 publications · 938 citations
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