Source-drain Engineering

Source-Drain Engineering is a device design methodology in Metal-Oxide-Semiconductor Field-Effect Transistors that involves the intentional modification of the source and drain regions' doping profiles, materials, or geometries to mitigate short-channel effects and enhance carrier transport, thereby improving transistor performance and scalability.

368

Publications

12.4K

Citations

1.7K

Authors

284

Institutions

Publications per year

2017–2026

59

Authors

1.7K

  1. YY
    Yee‐Chia Yeo

    National University of Singapore, Singapore

    21 publications · 627 citations

    14

    h-index

  2. GS
    Ganesh S. Samudra

    National University of Singapore, Singapore

    10 publications · 403 citations

    10

    h-index

  3. RL
    Roger Loo

    IMEC, Belgium

    10 publications · 266 citations

    10

    h-index

  4. ST
    Shinichi Takagi

    The University of Tokyo, Japan

    9 publications · 469 citations

    9

    h-index

  5. KC
    Krishna C. Saraswat

    Stanford University, United States

    8 publications · 259 citations

    8

    h-index

1–5 of 1.7K

Venues

  1. IEEE Electron Device Letters

    47 publications · 1.7K citations

    23

    h-index

  2. IEEE Transactions on Electron Devices

    46 publications · 1.6K citations

    21

    h-index

  3. Solid-State Electronics

    33 publications · 938 citations

    18

    h-index

  4. Superlattices and Microstructures

    11 publications · 346 citations

    11

    h-index

  5. Silicon

    12 publications · 255 citations

    11

    h-index

1–5