IEEE International Reliability Physics Symposium proceedings · 2009 · 14 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ReliabilityIntegrated Circuit DesignAmplificationBipolar Junction Transistor SimulationCmos Digital Circuit DesignCmos Logic CircuitsCmos ReliabilitySingle Event EffectsSoft ErrorsTemperature Sensitivity
Combinational logic soft errors are expected to be the dominant reliability issue for advanced technologies. One of the major factors affecting the soft-error rates is single-event transient (SET) pulse widths. The SET pulse widths, which are controlled by drift, diffusion, and parasitic bipolar transistor parameters, are a strong function of operating temperature. In this work, heavy-ion induced SET pulse widths are reported at temperatures ranging from 25deg to 100degC with an autonomous SET capture circuit. Experimental and simulation results in a 90 nm bulk CMOS technology indicate an increase as high as 37% in average SET pulse width with increasing operating temperature, with some pulses almost 2 ns long at higher temperatures. The increase in the SET pulse width can be explained by the dependence of bipolar amplification on temperature.
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