Extrusion Suppression of TSV Filling Metal by Cu-W Electroplating for Three-Dimensional Microelectronic Packaging

Through-Silicon Via (TSV)

Makoto Motoyoshi · Proceedings of the IEEE · 2009 · 474 citations

Engineering, Computer Engineering, Electrical Engineering +17

Transition from flip chip solder joint to 3D IC microbump: Its effect on microstructure anisotropy

K. N. Tu, Hsiang‐Yao Hsiao, Chih Chen · Microelectronics Reliability · 2012 · 186 citations

Engineering, Materials Engineering, Materials Science +15

Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication

A. Heryanto, Wahyuaji Narottama Putra, A. Trigg et al. · Journal of Electronic Materials · 2012 · 165 citations

Engineering, Materials Engineering, Materials Science +9

Measurement of stresses in Cu and Si around through-silicon via by synchrotron X-ray microdiffraction for 3-dimensional integrated circuits

Arief Suriadi Budiman, Hyun-Pyo Shin, Bum‐Joon Kim et al. · Microelectronics Reliability · 2011 · 143 citations

Engineering, Electrical Engineering, Materials Science +14

Cu pumping in TSVs: Effect of pre-CMP thermal budget

Ingrid De Wolf, Kristof Croes, Olalla Varela Pedreira et al. · Microelectronics Reliability · 2011 · 137 citations

Engineering, Materials Engineering, Materials Science +9