Applied Physics Letters · 2010 · 19 citations · 15 references
EngineeringIntegrated CircuitsMechanics Of MaterialsSilicon On InsulatorDefect ToleranceRelevant Iii-v SemiconductorsSemiconductor DeviceWafer BendingPiezoelectric MaterialElectronic PackagingWafer Bending ExperimentsComplimentary LogicMaterials ScienceMaterials EngineeringElectrical EngineeringSemiconductor TechnologyUniaxial StressSemiconductor Device FabricationPiezoelectricityMicroelectronicsApplied PhysicsUnixial StressHigh Strain Rate
In this work, effect of uniaxial stress is studied by wafer bending on p/n-channel candidates for III-V based complimentary logic. p-GaSb has 2× higher piezoresistance (π) coefficient than p-In0.53Ga0.47As, which combined with high hole-mobility in GaSb makes it an attractive candidate for III-V p-metal-oxide-semiconductor-field-effect-transistor. Limitation on maximum stress introduced by wafer bending is improved when the III-V channel is grown epitaxially on silicon. 250 MPa of stress is achieved by wafer bending on III-V channel grown on silicon substrate, which is 5× higher than maximum stress achieved on III-V substrate.
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Piezoresistance Effect in Germanium and Silicon
Charles S. Smith · Physical Review · 1954 · 2K citations
A Logic Nanotechnology Featuring Strained-Silicon
Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Electron Device Letters · 2004 · 511 citations
Electrical Engineering, Engineering, Flexible Electronics +12