Hole mobility in silicon inversion layers: Stress and surface orientation

Abstract

Hole transport in the p-type metal-oxide-semiconductor field-effect-transistor (p-MOSFET) inversion layer under arbitrary stress, surface, and channel orientation is investigated by employing a six-band k∙p model and finite difference formalism. The piezoresistance coefficients are calculated and measured at stresses up to 300MPa via wafer-bending experiments for stresses of technological importance: uniaxial and biaxial stresses on (001) and (110) surface oriented p-MOSFETs with ⟨110⟩ and ⟨111⟩ channels. With good agreement in the measured and calculated small stress piezoresistance coefficients, k∙p calculations are used to give physical insights into hole mobility enhancement at large stress (∼3GPa). The results show that the maximum hole mobility is similar for (001)∕⟨110⟩, (110)∕⟨110⟩, and (110)∕⟨111⟩ p-MOSFETs under uniaxial stress, although the enhancement factor is different. Strong quantum confinement and a low density of states cause less stress-induced mobility enhancement for (110) p-MOSFETs. For (001) p-MOSFETs, the dominant factor for the improved hole mobility is reduced conductivity effective mass at small stress and lower phonon scattering rate at large stress.