Si tunnel transistors with a novel silicided source and 46mV/dec swing

Kanghoon Jeon, Wei-Yip Loh, Pratik Patel, +11

SemiconductorsSemiconductor TechnologyElectrical EngineeringSemiconductor DeviceEngineering +11

Effective work function of Pt, Pd, and Re on atomic layer deposited HfO2

Diefeng Gu, Sandwip K. Dey, Prashant Majhi

Applied Physics Letters

Materials ScienceVacuum Work FunctionSurface CharacterizationEngineeringSurface Chemistry +11

Prospect of tunneling green transistor for 0.1V CMOS

Chenming Hu, Pratik Patel, Anupama Bowonder, +9

SemiconductorsElectrical EngineeringSemiconductor DeviceEngineeringVlsi Design +8

Nanoscale doping of InAs via sulfur monolayers

Johnny C. Ho, Alexandra C. Ford, Yu‐Lun Chueh, +7

Applied Physics Letters

Wide-bandgap SemiconductorEngineeringOptoelectronic DevicesSemiconductor DeviceSemiconductor Nanostructures +16

High Speed Memory Operation in Channel-Last, Back-gated Ferroelectric Transistors

Abhishek A. Sharma, B.S. Doyle, Hui Jae Yoo, +8

SemiconductorsElectrical EngineeringEngineeringSemiconductor ChannelNanoelectronics +9

Improved Electrical Characteristics of Ge-on-Si Field-Effect Transistors With Controlled Ge Epitaxial Layer Thickness on Si Substrates

Jungwoo Oh, Prashant Majhi, Hideok Lee, +7

IEEE Electron Device Letters

Electrical CharacteristicsNovel MosfetsElectrical EngineeringGe-on-si Field-effect TransistorsEngineering +10

Self-aligned n-channel metal-oxide-semiconductor field effect transistor on high-indium-content In0.53Ga0.47As and InP using physical vapor deposition HfO2 and silicon interface passivation layer

Injo Ok, H. Kim, M. Zhang, +11

Applied Physics Letters

Electrical EngineeringMaterial CharacteristicsEngineeringGood Transistor BehaviorBias Temperature Instability +6

Decoupling the Fermi-level pinning effect and intrinsic limitations on p-type effective work function metal electrodes

Huang-Chun Wen, Prashant Majhi, Kisik Choi, +12

Microelectronic Engineering

Materials ScienceElectrical EngineeringEngineeringIntrinsic LimitationsNanoelectronics +8

Integration of Dual Metal Gate CMOS on High-k Dielectrics Utilizing a Metal Wet Etch Process

Zhibo Zhang, S. C. Song, C. Huffman, +8

Electrochemical and Solid-State Letters

Materials ScienceElectrical EngineeringEngineeringNanoelectronicsOxide Electronics +12

Band-Engineered Low PMOS V<inf>T</inf> with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

H. R. Harris, Pankaj Kalra, Prashant Majhi, +16

EngineeringVlsi DesignIntegrated CircuitsSilicon On InsulatorDual Channel Scheme +15