High Speed Memory Operation in Channel-Last, Back-gated Ferroelectric Transistors

Abstract

Scaled ferroelectric transistors (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> =76 nm) in a back- gated configuration are fabricated with a channel-last process flow. Using this approach, optimization of the ferroelectric gate oxide film can be decoupled from that of the semiconductor channel to reduce parasitic interfaces. As a result, ferroelectric transistors with 3σ memory window for fast programming time of 10 ns (including an instantaneous read-after-write) at 1.8 V and high endurance of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cycles are demonstrated for the first time.