A robust spacer gate process for deca-nanometer high-frequency MOSFETs

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

C. Auth, S. Balakrishnan, M. Bost et al. · 2005 · 230 citations

Engineering, Computer Engineering, Electrical Engineering +17

A spacer patterning technology for nanoscale CMOS

Yang‐Kyu Choi, Tsu-Jae King, Chenming Hu · IEEE Transactions on Electron Devices · 2002 · 207 citations

Engineering, Electrical Engineering, Materials Science +17

An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

C.H. Diaz, Hun-Jan Tao, Yao-Ching Ku et al. · IEEE Electron Device Letters · 2001 · 148 citations

Engineering, Electrical Engineering, Microelectronics +16

Exposure of 38 nm period grating patterns with extreme ultraviolet interferometric lithography

H. H. Solak, Di He, W. Li et al. · Applied Physics Letters · 1999 · 120 citations · Full text

Engineering, Materials Engineering, Materials Science +11

Nanometer-scale linewidth fluctuations caused by polymer aggregates in resist films

Toru Yamaguchi, Hideo Namatsu, Masao Nagase et al. · Applied Physics Letters · 1997 · 105 citations

Natural Sciences, Materials Engineering, Materials Science +17