Yao-Ching Ku

An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

C.H. Diaz, Hun-Jan Tao, Yao-Ching Ku et al. · IEEE Electron Device Letters · 2001 · 148 citations

Device Modeling, Electrical Engineering, Gate Length +15

A 16nm FinFET CMOS technology for mobile SoC and computing applications

Shien-Yang Wu, Chi-Hsien Lin, M.C. Chiang et al. · 2013 · 146 citations

Low-power Electronics, System On Chip, Electrical Engineering +15

A 7nm CMOS platform technology featuring 4^th generation FinFET transistors with a 0.027um² high density 6-T SRAM cell for mobile SoC applications

Shien-Yang Wu, C.Y. Lin, M.C. Chiang et al. · 2016 · 124 citations

Low-power Electronics, Electrical Engineering, Cmos Platform Technology +13

An enhanced 16nm CMOS technology featuring 2<sup>nd</sup> generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

Shien-Yang Wu, C.Y. Lin, M.C. Chiang et al. · 2014 · 61 citations

Low-power Electronics, Low Power, Electrical Engineering +14

A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications

K.K. Young, S.Y. Wu, Chung-Cheng Wu et al. · 2002 · 50 citations

Engineering, Vlsi Design, Computer Architecture +18