S.Y. Wu

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

P. Agnello, T. Ivers, C. Warm et al. · 2006 · 115 citations

Engineering, Vlsi Design, Enhanced Strain +21

Virtual metrology: a solution for wafer to wafer advanced process control

P. T. Chen, S.Y. Wu, Junshien Lin et al. · 2005 · 97 citations

Virtual Manufacturing, Engineering, Computer Architecture +19

A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications

K.K. Young, S.Y. Wu, Chung-Cheng Wu et al. · 2002 · 50 citations

Engineering, Vlsi Design, Computer Architecture +18

A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications

Chung-Cheng Wu, Yuet‐Kin Leung, C. S. Chang et al. · 2003 · 46 citations

Engineering, Vlsi Design, Power Electronics +17

Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond

Chih‐Hao Chang, Vincent S. Chang, K.H. Pan et al. · 2022 International Electron Devices Meeting (IEDM) · 2022 · 31 citations

Electrical Engineering, Physical Design (Electronics), Engineering +15