Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond

Abstract

To continue contacted gate pitch scaling, transistor with improved electrostatics, gate stack innovation, and appropriate contact scheme along with improved process control to reduce variability are all indispensable factors. As gate pitch scales into the sub-50nm regime, electrostatics of FinFET architecture, spacer material, and traditional contact scheme all approach their engineering limits. Here we report a leading-edge CMOS technology developed at 45nm contacted gate pitch that successfully incorporates optimized fin profile, low-k spacer and self-aligned contact scheme. The process robustness is validated by a logic test chip with >3.5 billion transistor gate count and fully functioning 256Mb HC/HD SRAM macros. The demonstrated high-density SRAM cell size of $0.0199 \mu \mathrm{m}^{2}$ is the smallest reported to date.