C.J. Lin

A 7nm CMOS platform technology featuring 4^th generation FinFET transistors with a 0.027um² high density 6-T SRAM cell for mobile SoC applications

Shien-Yang Wu, C.Y. Lin, M.C. Chiang et al. · 2016 · 129 citations

Engineering, Computer Engineering, Electrical Engineering +13

Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond

Chih‐Hao Chang, Vincent S. Chang, K.H. Pan et al. · 2022 International Electron Devices Meeting (IEDM) · 2022 · 31 citations

Engineering, Computer Engineering, Electrical Engineering +16

High performance/reliability Cu interconnect with selective CoWP cap

T. Ko, Chih-Sheng Chang, S.W. Chou et al. · 2004 · 12 citations

Engineering, Electrical Engineering, Materials Science +17

Direct plating of Cu on ALD TaN for 45nm-node Cu BEOL metallization

Chun-Hsing Shih, H.W. Su, C.J. Lin et al. · 2005 · 10 citations

Natural Sciences, Materials Engineering, Materials Science +13