C.Y. Lin

A 7nm CMOS platform technology featuring 4^th generation FinFET transistors with a 0.027um² high density 6-T SRAM cell for mobile SoC applications

Shien-Yang Wu, C.Y. Lin, M.C. Chiang et al. · 2016 · 129 citations

Engineering, Computer Engineering, Electrical Engineering +13

An enhanced 16nm CMOS technology featuring 2<sup>nd</sup> generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

Shien-Yang Wu, C.Y. Lin, M.C. Chiang et al. · 2014 · 62 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications

Shien-Yang Wu, M.C. Chiang, C.Y. Lin et al. · 2022 International Electron Devices Meeting (IEDM) · 2022 · 56 citations

Engineering, Electrical Engineering, High-performance Computing +17

Demonstration of a sub-0.03 um²high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node

Shien-Yang Wu, C.Y. Lin, M.C. Chiang et al. · 2016 · 21 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM

Shien-Yang Wu, Chung-Cheng Chou, C.Y. Lin et al. · 2007 · 19 citations

Engineering, Computer Engineering, Electrical Engineering +16