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A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications
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2022
Year
Low-power ElectronicsElectrical EngineeringCmos Platform TechnologyEngineeringVlsi DesignHigh-speed ElectronicsEnhanced Power EfficiencyFinflex™ Platform TechnologyAdvanced Packaging (Semiconductors)Computer ArchitectureComputer EngineeringTraditional Finfet TechnologiesIntegrated CircuitsMobile SocMicroelectronicsBeyond CmosPower-aware DesignTechnology Co-optimization
The industry fastest time-to-manufacturability 3nm CMOS platform technology is presented. FinFlex™ with standard cells consisting of different fin configurations is introduced for the first time to offer the critical design flexibility for better power efficiency and performance optimization compared to traditional FinFET technologies. An aggressive scaling of ~1.6X logic density increase, 18% speed improvement and 34% power reduction are achieved over our previous 5nm CMOS process. This FinFlex™ platform technology provides the best-in-class PPAC values to fully unleash product innovations in 5G and HPC applications.