J.J. Liaw - Concepedia

Author

J.J. Liaw

Taiwan Semiconductor Manufacturing Company (Taiwan)

Also Known As

J. J. Liaw, J.J. Liaw, Jhon-Jhy Liaw, Jonathan Chang

Publications

Citations

H-Index

Concepts

All Affiliations

Taiwan Semiconductor Manufacturing Company (Taiwan)Taiwan Semiconductor Manufacturing Company (United States)

About

J.J. Liaw is an author at Taiwan Semiconductor Manufacturing Company (Taiwan) specializing in electrical engineering, vlsi design, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	17	20	846
2	Electrical Engineering	17	20	846
3	Computer Engineering	16	18	812
4	Applied Physics	7	7	209
5	Physics	1	1	66

J.J. Liaw

Publications

869

Citations

H-Index

Page 1

	Year	Citations
A 16nm FinFET CMOS technology for mobile SoC and computing applications Shien-Yang Wu, Chi-Hsien Lin, M.C. Chiang, Low-power ElectronicsSystem On ChipElectrical EngineeringEngineeringVlsi Design	2013	146
A 7nm CMOS platform technology featuring 4<sup>th</sup> generation FinFET transistors with a 0.027um<sup>2</sup> high density 6-T SRAM cell for mobile SoC applications Shien-Yang Wu, C.Y. Lin, M.C. Chiang, Low-power ElectronicsElectrical EngineeringCmos Platform TechnologyMobile Soc ApplicationsVlsi Design	2016	124
Leakage scaling in deep submicron CMOS for SoC Yo‐Sheng Lin, Chung-Cheng Wu, Chih-Sheng Chang, IEEE Transactions on Electron Devices Hardware SecurityLow-power ElectronicsElectrical EngineeringSemiconductor DeviceEngineering	2002	66
A 25-nm gate-length FinFET transistor module for 32nm node Chang-Yun Chang, Tsung-Lin Lee, C. Wann, Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignTechnology Scaling	2009	62
An enhanced 16nm CMOS technology featuring 2<sup>nd</sup> generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications Shien-Yang Wu, C.Y. Lin, M.C. Chiang, Low-power ElectronicsLow PowerElectrical EngineeringHigh DensityEngineering	2014	61
A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications Shien-Yang Wu, M.C. Chiang, C.Y. Lin, 2022 International Electron Devices Meeting (IEDM) Low-power ElectronicsElectrical EngineeringCmos Platform TechnologyEngineeringVlsi Design	2022	49
A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process Shien-Yang Wu, J.J. Liaw, Chih‐Yung Lin, Symposium on VLSI Technology Low-power ElectronicsMb Sram Test-chipElectrical EngineeringEngineeringVlsi Design	2006	42
32nm gate-first high-k/metal-gate technology for high performance low power applications C.H. Diaz, Kenichi Gotō, H.T. Huang, Low-power ElectronicsElectrical EngineeringSemiconductor DeviceEngineeringVlsi Design	2008	36
A 0.18 μm CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications C.H. Diaz, K.L. Young, Johnny Hsu, Low-power ElectronicsElectrical EngineeringμM CmosEngineeringVlsi Design	2003	36
Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond Chih‐Hao Chang, Vincent S. Chang, K.H. Pan, 2022 International Electron Devices Meeting (IEDM) Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignMicrofabrication	2022	31

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