An enhanced 16nm CMOS technology featuring 2<sup>nd</sup> generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

Abstract

Advancing the state-of-the-art 16nm technology reported last year, an enhanced 16nm CMOS technology featuring the second generation FinFET transistors and advanced Cu/low-k interconnect is presented. Core devices are re-optimized to provide additional 15% speed boost or 30% power reduction. Device overdrive capability is also extended by 70mV through reliability enhancement. Superior 128Mb High Density (HD) SRAM Vccmin capability of 450mV is achieved with variability reduction for the first time. Metal capacitance reduction by ∼9% is realized with advanced interconnect scheme to enable dynamic power saving.