T. Miyashita - Concepedia

Author

T. Miyashita

Taiwan Semiconductor Manufacturing Company (Taiwan)

Also Known As

T. Miyashita, Toshihiko MIYASHITA, Toshihiko Miyashita, U. Celano

Publications

662

Citations

H-Index

Concepts

All Affiliations

Taiwan Semiconductor Manufacturing Company (Taiwan)Fujitsu (Japan)Applied Materials (United States)

About

T. Miyashita is an author at Taiwan Semiconductor Manufacturing Company (Taiwan) specializing in electrical engineering, microelectronics, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	10	10	448
2	Applied Physics	4	4	58
3	Medicine	1	1	91
4	Natural Sciences	1	1	91
5	Biochemistry	1	1	91

T. Miyashita

Publications

577

Citations

H-Index

Page 1

	Year	Citations
A 16nm FinFET CMOS technology for mobile SoC and computing applications Shien-Yang Wu, Chi-Hsien Lin, M.C. Chiang, Low-power ElectronicsSystem On ChipElectrical EngineeringEngineeringVlsi Design	2013	146
A 7nm CMOS platform technology featuring 4<sup>th</sup> generation FinFET transistors with a 0.027um<sup>2</sup> high density 6-T SRAM cell for mobile SoC applications Shien-Yang Wu, C.Y. Lin, M.C. Chiang, Low-power ElectronicsElectrical EngineeringCmos Platform TechnologyMobile Soc ApplicationsVlsi Design	2016	124
Structural and Conformational Studies of (Ile7) and (Leu7)Surfactins from Bacillus subtilis natto. Hideji Itokawa, T. Miyashita, Hiroshi Morita, Chemical and Pharmaceutical Bulletin Bacillus SubtilisBiochemistryBiomolecular Structure PredictionProtein FoldingNatural Sciences	1994	91
An enhanced 16nm CMOS technology featuring 2<sup>nd</sup> generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications Shien-Yang Wu, C.Y. Lin, M.C. Chiang, Low-power ElectronicsLow PowerElectrical EngineeringHigh DensityEngineering	2014	61
A study of highly scalable DG-FinDRAM Eiji Yoshida, T. Miyashita, Tetsu Tanaka IEEE Electron Device Letters Scalable Dg-findramFinfet DramElectrical EngineeringEngineeringHardware Acceleration	2005	25
High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology T. Miyashita, Keiji Ikeda, Y. S. Kim, EngineeringVlsi DesignEmerging Memory TechnologyComputer ArchitectureIntegrated Circuits	2007	22
Demonstration of a sub-0.03 um<sup>2</sup>high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node Shien-Yang Wu, C.Y. Lin, M.C. Chiang, Low-power ElectronicsScaled Bulk FinfetsElectrical EngineeringMobile Soc ApplicationsEngineering	2016	21
Electron-assisted switching in FeFETs: Memory window dynamics – retention – trapping mechanisms and correlation Milan Pešić, Bastien Beltrando, Andrea Padovani, 2022 IEEE International Reliability Physics Symposium (IRPS)	2022	15
Scaled, Novel Effective Workfunction Metal Gate Stacks for Advanced Low-V<sub>T</sub>, Gate-All-Around Vertically Stacked Nanosheet FETs with Reduced Vertical Distance between Sheets A. Veloso, Eddy Simoen, Antônio Honorato De Oliveira, Extended Abstracts of the 2019 International Conference on Solid State Devices and Materials Low-power ElectronicsMaterials ScienceElectrical EngineeringAdvanced Low-vReduced Vertical Distance	2019	14
Experimental evaluation of depth-dependent lateral standard deviation for various ions in a-Si from one-dimensional tilted implantation profiles T. Miyashita, Ken Suzuki IEEE Transactions on Electron Devices Various IonsImpurity ProfilesElectrical EngineeringIon ImplantationEngineering	1999	13

Page 1