Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Haining Yang, R. Malik, Y. Li, +47

Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignAdvanced Packaging (Semiconductors) +11

High performance 14nm SOI FinFET CMOS technology with 0.0174µm<sup>2</sup> embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai, +95

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

P. Agnello, T. Ivers, C. Warm, +77

EngineeringVlsi DesignEnhanced StrainPorous Low-k BeolIntegrated Circuits +19

Silicides and local interconnections for high-performance VLSI applications

R. Mann, L. A. Clevenger, P. Agnello, +1

IBM Journal of Research and Development

Electrical EngineeringElectronic DevicesEngineeringVlsi DesignLocal Interconnections +10

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried, +51

High-performance Soi TechnologyEngineeringVlsi DesignComputer ArchitectureInterconnect (Integrated Circuits) +14

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Siddarth Krishnan, U. Kwon, N. Moumen, +59

Sige ChannelsLow Power ApplicationsEngineeringVlsi DesignIntegrated Circuits +14

CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-μm CMOS technology

H.‐S. Philip Wong, R.T. Chang, E.F. Crabbé, +1

IEEE Transactions on Electron Devices

Experimental ResultsEngineering0.25-μM Cmos TechnologyMixed-signal Integrated CircuitImage Processor +8

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta, +79

Electrical EngineeringEngineeringVlsi DesignAdvanced Packaging (Semiconductors)Nm Soi Technology +13

A 7nm CMOS technology platform for mobile and high performance compute application

B. Jagannathan, Akihisa Ogino, D. Jaeger, +149

EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsHardware Systems +15

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

W.-H. Lee, Anya M. Waite, H. Nii, +53

EngineeringVlsi DesignIntegrated CircuitsSilicon On InsulatorHigh Performance 65 +17