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L. Chang, David Fried, J. M. Hergenrother, +9

Low-power ElectronicsNon-volatile MemoryElectrical EngineeringEngineeringVlsi Design +10

Extension and source/drain design for high-performance finFET devices

J. Kedzierski, M. Ieong, E. Nowak, +6

IEEE Transactions on Electron Devices

Low-power ElectronicsExtension ImplantsElectrical EngineeringEngineeringVlsi Design +12

Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation

J. Kedzierski, E. Nowak, T. Kanarsky, +21

Electrical EngineeringEngineeringTotal Gate SilicidationNanoelectronicsMetal-gate Finfet +7

Hybrid-orientation technology (HOT): opportunities and challenges

Min Yang, V. Chan, K. Chan, +9

IEEE Transactions on Electron Devices

EngineeringSilicon MosfetsSilicon On InsulatorAdvanced DesignSocial Sciences +17

Human–machine collaboration for improving semiconductor process development

Keren J. Kanarik, Wojciech T. Osowiecki, Yu Lu, +6

Nature

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried, +51

High-performance Soi TechnologyEngineeringVlsi DesignComputer ArchitectureInterconnect (Integrated Circuits) +14

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

L.T. Su, John Pellerin, Shih-Fen Huang, +42

EngineeringVlsi DesignSilicon On InsulatorInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors) +14

Improved independent gate N-type FinFET fabrication and characterization

David Fried, J.S. Duster, Kevin Kornegay

IEEE Electron Device Letters

Electrical EngineeringEngineeringMicrofabricationNanoelectronicsElectronic Engineering +9

High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

J. Kedzierski, David Fried, E. Nowak, +21

Low-power ElectronicsElectrical EngineeringHigh-performance Symmetric-gateDouble-gate Finfet DevicesVlsi Design +9

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

W.-H. Lee, Anya M. Waite, H. Nii, +53

EngineeringVlsi DesignIntegrated CircuitsSilicon On InsulatorHigh Performance 65 +17