C-H. Lin

High performance 14nm SOI FinFET CMOS technology with 0.0174µm ² embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 129 citations

Engineering, Computer Engineering, Electrical Engineering +9

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried et al. · 2012 · 89 citations

Engineering, Computer Engineering, Electrical Engineering +17

Ti and NiPt/Ti liner silicide contacts for advanced technologies

Praneet Adusumilli, Emre Alptekin, M. Raymond et al. · 2016 · 31 citations

Engineering, Electrical Engineering, Materials Science +14

E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology

M. Shamanna, Eli Abuayob, G. Aenuganti et al. · 2023 · 26 citations

Engineering, Computer Engineering, Electrical Engineering +17

A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

T. Yamashita, S. Mehta, Veeraraghavan Basker et al. · 2015 · 21 citations

Engineering, Electrical Engineering, Materials Science +17