C. Ortolland

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

T. Chiarella, Liesbeth Witters, A. Mercha et al. · Solid-State Electronics · 2010 · 120 citations

Electrical Engineering, Physical Design (Electronics), Engineering +8

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried et al. · 2012 · 89 citations

High-performance Soi Technology, Engineering, Vlsi Design +16

Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors

Stphane Orain, Vincent Fiori, D. Villanueva et al. · IEEE Transactions on Electron Devices · 2007 · 44 citations

Engineering, Transistor Improvement, Cesl Parts +16

Stress Memorization Technique (SMT) Optimization for 45nm CMOS

C. Ortolland, P. Morin, C. Chaton et al. · 2006 · 38 citations

Materials Engineering, Electrical Engineering, Engineering +11

Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

C. Ortolland, Yasutoshi Okuno, Peter Verheyen et al. · IEEE Transactions on Electron Devices · 2009 · 31 citations

Engineering, Vlsi Design, Maskless Smt Integration +16