Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

T. Chiarella, Liesbeth Witters, A. Mercha, +13

Solid-State Electronics

Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignTechnology Scaling +6

22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

P. Chang, C. Ortolland, David Fried, +51

High-performance Soi TechnologyEngineeringVlsi DesignComputer ArchitectureInterconnect (Integrated Circuits) +14

Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors

Stphane Orain, Vincent Fiori, D. Villanueva, +2

IEEE Transactions on Electron Devices

EngineeringTransistor ImprovementCesl PartsResidual StressInterconnect (Integrated Circuits) +14

Stress Memorization Technique (SMT) Optimization for 45nm CMOS

C. Ortolland, P. Morin, C. Chaton, +7

Materials EngineeringElectrical EngineeringEngineeringVlsi DesignCircuit Design +9

Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

C. Ortolland, Yasutoshi Okuno, Peter Verheyen, +5

IEEE Transactions on Electron Devices

EngineeringVlsi DesignMaskless Smt IntegrationComputer ArchitectureIntegrated Circuits +14

Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology

C. Ortolland, Erik Rosseel, Naoto Horiguchi, +14

EngineeringVlsi DesignLaser AnnealSilicon On InsulatorInterconnect (Integrated Circuits) +15

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

T. Chiarella, Liesbeth Witters, A. Mercha, +16

System On ChipElectrical EngineeringEngineeringVlsi DesignMulti-gate Architecture +9

Nonuniform Mobility-Enhancement Techniques and Their Impact on Device Performance

F. Payet, C. Ortolland, T. Skotnicki

IEEE Transactions on Electron Devices

Nonuniform Mobility-enhancement TechniquesEngineeringMobile CommunicationSemiconductor DevicePhysical Design (Electronics) +15

Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology

C. Ortolland, S. Orain, José M. de la Rosa, +5

EngineeringTransistor Layout RulesSemiconductor DevicePhysical Design (Electronics)Nanoelectronics +15

Process technology for IBM 14-nm processor designs featuring silicon-on-insulator FinFETs

S. R. Stiffler, Rakesh Ramachandran, W.K. Henson, +7

IBM Journal of Research and Development

EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsSilicon On Insulator +15