C. Chaton

A conventional 45nm CMOS node low-cost platform for general purpose and low power applications

F. Arnaud, M.T. Basso, D. Sotta et al. · 2004 · 42 citations

Stress Memorization Technique (SMT) Optimization for 45nm CMOS

C. Ortolland, P. Morin, C. Chaton et al. · 2006 · 38 citations

Materials Engineering, Electrical Engineering, Engineering +11

Integration of fluorine-doped silicon oxide in copper pilot line for 0.12-μm technology

J.-P. Reynard, C. Vérove, E. Sabouret et al. · Microelectronic Engineering · 2002 · 28 citations

Materials Engineering, 0.12-μM Technology, Electrical Engineering +10

Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels

C. Gallon, C. Fenouillet-Béranger, S. Denorme et al. · Japanese Journal of Applied Physics · 2006 · 26 citations

Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications

F. Roy, Andrej Suler, Thomas Dalleau et al. · Sensors · 2020 · 21 citations · Full text

Engineering, Optoelectronic Devices, Integrated Circuits +16