Vincent Fiori - Concepedia

Author

Vincent Fiori

STMicroelectronics (France)

Also Known As

Fiori, V., Fiori, Vincent, V Fiori, V. Fiori, Vincent Fiori

Publications

477

Citations

H-Index

Concepts

All Affiliations

STMicroelectronics (France)Philips (France)Commissariat à l'Énergie Atomique et aux Énergies Alternatives Laboratoire d'Électronique des Technologies de l'Information Université Grenoble Alpes

About

Vincent Fiori is an author at STMicroelectronics (France) specializing in engineering, microelectronics, and electronic packaging.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	13	15	295
2	Applied Physics	9	9	186
3	Electrical Engineering	9	9	200
4	Computer Engineering	4	4	59
5	Natural Sciences	1	1	16

Vincent Fiori

Publications

332

Citations

H-Index

Page 1

	Year	Citations
Method for Managing the Stress Due to the Strained Nitride Capping Layer in MOS Transistors Stphane Orain, Vincent Fiori, D. Villanueva, IEEE Transactions on Electron Devices EngineeringTransistor ImprovementCesl PartsResidual StressInterconnect (Integrated Circuits)	2007	44
A multi scale finite element methodology to evaluate wire bond pad architectures Vincent Fiori, S. Orain EngineeringMechanical EngineeringMultiscale MaterialStructural MechanicsStructural Optimization	2005	40
Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels C. Gallon, C. Fenouillet-Béranger, S. Denorme, Japanese Journal of Applied Physics	2006	26
3D Multi Scale Modeling of Wire Bonding Induced Peeling in Cu/Low-k Interconnects: Application of an Energy Based Criteria and Correlations with Experiments Vincent Fiori, Lau Teck Beng, Susan Downey, EngineeringMechanical EngineeringCu/low-k InterconnectsStructural EngineeringInterconnect (Integrated Circuits)	2007	25
Cu/SiO<inf>2</inf> hybrid bonding: Finite element modeling and experimental characterization C. Sart, Rafaël Estevez, Vincent Fiori, 2016 6th Electronic System-Integration Technology Conference (ESTC) EngineeringIntegrated CircuitsThermal AnnealingInterconnect (Integrated Circuits)Wafer Scale Processing	2016	25
Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits P. Coudrain, Papa Momar Souaré, R. Prieto, IEEE Design and Test EngineeringEnergy EfficiencyIntegrated CircuitsInterconnect (Integrated Circuits)Refrigeration	2015	18
Integration of a mechanically reliable 65-nm node technology for low-k and ULK interconnects with various substrate and package types Cindy Goldberg, Susan Downey, Vincent Fiori, EngineeringMechanical EngineeringFlip-chip PackagesInterconnect (Integrated Circuits)Weak Bulk	2005	17
Ultra-Thin Fully Depleted SOI Devices with Thin BOX, Ground Plane and Strained Liner Booster C. Gallon, A. Vandooren, F. Payet, Proceedings - IEEE International SOI Conference/Proceedings EngineeringThin BoxIntegrated CircuitsInterconnect (Integrated Circuits)Semiconductor Device	2006	17
New challenges and opportunities for 3D integrations J. Michailos, P. Coudrain, A. Farcy, EngineeringDevice IntegrationComputer ArchitectureHigh Densities3D Modeling	2015	16
Through-silicon via-induced strain distribution in silicon interposer B. Vianne, Marie‐Ingrid Richard, S. Escoubas, Applied Physics Letters EngineeringIntegrated CircuitsSilicon On InsulatorInterconnect (Integrated Circuits)Ion Implantation	2015	15

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