E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology

Abstract

PowerVia Technology [1] is a novel innovation to extend Moore’s Law scaling by having Power Delivery on the backside. This paper presents the pre & post-silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of >90% in large areas of the core while showing >5% Frequency benefit in Silicon due to reduced IR drop. Successful Post-Silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristic of the PowerVia test-chip is in line with higher power densities expected from logic scaling.