Y. Li

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

J. Mandelman, R.H. Dennard, G. Bronner et al. · IBM Journal of Research and Development · 2002 · 262 citations

Non-volatile Memory, Engineering, Dynamic Random-access Memory +16

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Haining Yang, R. Malik, Y. Li et al. · 2005 · 142 citations

Electrical Engineering, Physical Design (Electronics), Engineering +13

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

P. Agnello, T. Ivers, C. Warm et al. · 2006 · 115 citations

Engineering, Vlsi Design, Enhanced Strain +21

A high performance 90nm SOI technology with 0.992 μm/sup 2/ 6T-SRAM cell

Mukesh Khare, S.H. Ku, R. A. Donaton et al. · 2003 · 43 citations

Low-power Electronics, Materials Science, Electrical Engineering +14

High performance bulk planar 20nm CMOS technology for low power mobile applications

Huiling Shang, S. Jain, E. Josse et al. · 2012 · 26 citations

Low-power Electronics, High Density, Electrical Engineering +14