G. Bronner

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

J. Mandelman, R.H. Dennard, G. Bronner et al. · IBM Journal of Research and Development · 2002 · 269 citations

Engineering, Computer Engineering, Electrical Engineering +17

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Haining Yang, R. Malik, Y. Li et al. · 2005 · 142 citations

Engineering, Electrical Engineering, Manufacturing Engineering +11

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta et al. · 2005 · 65 citations

Engineering, Computer Engineering, Electrical Engineering +17

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

W.-H. Lee, Anya M. Waite, H. Nii et al. · 2006 · 55 citations

Engineering, Computer Engineering, Electrical Engineering +17

Relaxation Effect in RRAM Arrays: Demonstration and Characteristics

Chen Wang, Huaqiang Wu, Bin Gao et al. · IEEE Electron Device Letters · 2015 · 52 citations

Engineering, Electrical Engineering, Materials Science +16