Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

TLDR

DRAM scaling beyond the 0.10‑µm generation faces significant challenges, as traditional array‑access transistor and capacitor techniques hit limits, requiring major innovations in operating mode, structure, and processing, while options such as low‑voltage operation, vertical MOSFETs, and novel capacitor designs remain uncertain. The paper examines how DRAM scaling requirements interrelate and explores potential solutions. The study focuses on trench‑capacitor DRAM technology as a promising approach.

Abstract

Significant challenges face DRAM scaling toward and beyond the 0.10-µm generation. Scaling techniques used in earlier generations for the array-access transistor and the storage capacitor are encountering limitations which necessitate major innovation in electrical operating mode, structure, and processing. Although a variety of options exist for advancing the technology, such as low-voltage operation, vertical MOSFETs, and novel capacitor structures, uncertainties exist about which way to proceed. This paper discusses the interrelationships among the DRAM scaling requirements and their possible solutions. The emphasis is on trench-capacitor DRAM technology.