C. Radens

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

J. Mandelman, R.H. Dennard, G. Bronner et al. · IBM Journal of Research and Development · 2002 · 269 citations

Engineering, Computer Engineering, Electrical Engineering +17

Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells

A.J. Bhavnagarwala, Stephen Kosonocky, C. Radens et al. · 2006 · 162 citations

Engineering, Computer Engineering, Electrical Engineering +17

High performance 14nm SOI FinFET CMOS technology with 0.0174µm ² embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 129 citations

Engineering, Computer Engineering, Electrical Engineering +9

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

A.J. Bhavnagarwala, Stephen Kosonocky, C. Radens et al. · IEEE Journal of Solid-State Circuits · 2008 · 94 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

Harold Pilo, Igor Arsovski, Kevin Batson et al. · IEEE Journal of Solid-State Circuits · 2011 · 79 citations

Engineering, Computer Engineering, Electrical Engineering +14