A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Fluctuation limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring local stochastic distributions of 65-nm PDSOI CMOS SRAM cell storage node voltages during Read, Write, and Retention modes of operation. These measurements reveal insights into terminal voltage dependencies of cell margin distributions—observations that are engaged to increase cell immunity to random <formula><tex>${\rm V_T}$</tex> </formula> fluctuations by <emphasis emphasistype="boldital">several</emphasis> orders of magnitude by biasing the cell terminal voltages dynamically with a Read-Write asymmetry. Combinations of circuit techniques implementing these dynamic cell biasing schemes are demonstrated in a 9kb<formula formulatype="inline"><tex>$\, \times\,$</tex></formula>74b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST. Measurements demonstrate these techniques to enable <formula> <tex>${\rm V_{MIN}}$</tex></formula> <emphasis emphasistype="boldital">reductions of over 200 mV—lowering measured</emphasis> <formula><tex>${\rm V_{MIN}}$</tex> </formula> <emphasis emphasistype="boldital">to 0.54 V and 0.38 V/0.50 V for single and dual</emphasis> <formula formulatype="inline"><tex>$V_{DD}$</tex> </formula> <emphasis emphasistype="boldital">implementations, respectively.</emphasis> The techniques consume a 10%–12% overhead in area, impact performance marginally (<formula formulatype="inline"><tex>$≪ $</tex></formula>5%) and also enable over 50% reduction in cell leakage. </para>