Y.H. Chan - Concepedia

Author

Y.H. Chan

IBM Research - Thomas J. Watson Research Center ORCID

Also Known As

Y. Chan, Y. H. Chan, Y.-H. Chan, Y.H. Chan, Yiu Chan, Yiu Wai Chan, Yu-Kai Chan, Yuen Chan, Yuen H Chan, Yuen H. Chan

Publications

905

Citations

H-Index

Concepts

All Affiliations

IBM Research - Thomas J. Watson Research Center IBM (United States)Poughkeepsie Public Library District IBM (Germany)IBM Research - Austin

About

Y.H. Chan is an author at IBM Research - Thomas J. Watson Research Center specializing in vlsi design, computer engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	16	24	778
2	Computer Engineering	16	24	778
3	Electrical Engineering	15	21	727
4	Applied Physics	3	3	169
5	Computer Science	2	2	39

Y.H. Chan

Publications

821

Citations

H-Index

Page 1

	Year	Citations
Design of the Power6 Microprocessor Joshua Friedrich, B.D. McCredie, N. James, Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference EngineeringVlsi DesignComputer ArchitectureTransistor Dual-core MicroprocessorIntegrated Circuits	2007	114
A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing A.J. Bhavnagarwala, Stephen Kosonocky, C. Radens, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringVlsi DesignEmerging Memory TechnologyApplied Physics	2008	94
6.6+ GHz Low Vmin, read and half select disturb-free 1.2 Mb SRAM R. Houle, Kevin Batson, D. Rodko, Low-power ElectronicsElectrical EngineeringGhz Low VminFunctional ReadVlsi Design	2007	59
A 400-MHz S/390 microprocessor Charles F. Webb, C.J. Anderson, L. Sigal, IEEE Journal of Solid-State Circuits Hardware SecuritySystem On ChipElectrical EngineeringChip SizeEngineering	1997	55
A transregional CMOS SRAM with single, logic V/sub DD/ and dynamic power rails A.J. Bhavnagarwala, Stephen Kosonocky, S. P. Kowalczyk, Hardware SecurityLow-power ElectronicsElectrical EngineeringSram OperationEngineering	2004	48
Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell Subhas Chandra Mukhopadhyay, D. Plass, Y.H. Chan, Non-volatile MemoryElectrical EngineeringVariability AnalysisVlsi DesignEngineering	2004	43
A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing A.J. Bhavnagarwala, Stephen Kosonocky, Y.H. Chan, Low-power ElectronicsElectrical EngineeringCell LeakageEngineeringVlsi Design	2007	39
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics Rajiv Joshi, Saibal Mukhopadhyay, D. Plass, IEEE Journal of Solid-State Circuits Non-volatile MemoryElectrical EngineeringSub-90 Nm Low-powerEngineeringVlsi Design	2009	32
Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System J. Warnock, Yiu-Hing Chan, Seán Carey, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignComputer ArchitectureChip Design MethodologyIntegrated Circuits	2011	30
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module J. Warnock, Y.H. Chan, H. Harrer, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignElectronic DesignPhysical DesignComputer Architecture	2013	30

Page 1