5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8<sup>TM</sup> microprocessor

Zeynep Toprak-Deniz, Michael Sperling, John F. Bulzacchelli, +12

Electrical EngineeringPower-aware ComputingVoltage Regulator ModulesEngineeringEnergy Management +13

Design of the Power6 Microprocessor

Joshua Friedrich, B.D. McCredie, N. James, +14

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

EngineeringVlsi DesignComputer ArchitectureTransistor Dual-core MicroprocessorIntegrated Circuits +18

Design and implementation of the POWER5™ microprocessor

J. Clabes, Joshua Friedrich, M. Sweet, +18

EngineeringVlsi DesignEnergy EfficiencyComputer ArchitectureProcessor Architecture +14

Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor

N. James, P.J. Restle, Joshua Friedrich, +2

Low-power ElectronicsElectrical EngineeringManycore ProcessorEngineeringVlsi Design +13

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection

Michael S. Floyd, P.J. Restle, Michael Sperling, +7

Low-power ElectronicsPower-aware ComputingElectrical EngineeringAdaptive Clock StrategyEngineering +10

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

Eric Fluhr, Steve Baumgartner, D. Boerstler, +27

IEEE Journal of Solid-State Circuits

EngineeringCore ThroughputEnergy EfficiencyComputer ArchitecturePower Optimization +17

5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth

Eric Fluhr, Joshua Friedrich, Daniel Dreps, +17

EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsAdvanced Packaging (Semiconductors) +14

Design and Implementation of the POWER6 Microprocessor

Benjamin Stolt, Yonatan Mittlefehldt, Sanjay Dubey, +4

IEEE Journal of Solid-State Circuits

Circuit MethodologyEngineeringVlsi DesignComputer ArchitectureIbm Power6 Processor +16

5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8<sup>TM</sup> microprocessor

P.J. Restle, David Shan, David Hogenmiller, +7

Low-power ElectronicsSystem On ChipElectrical EngineeringWide-frequency-range Resonant ClockEngineering +11

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4

Christopher González, Michael S. Floyd, Eric Fluhr, +20

IEEE Journal of Solid-State Circuits

Engineering16-Gb/s Pcie Gen4Computer ArchitectureIntegrated CircuitsProcessor Architecture +18