Michael Sperling

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8<sup>TM</sup> microprocessor

Zeynep Toprak-Deniz, Michael Sperling, John F. Bulzacchelli et al. · 2014 · 119 citations

Electrical Engineering, Power-aware Computing, Voltage Regulator Modules +15

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

J. Barth, Kavita Nair, Nianzheng Cao et al. · IEEE Journal of Solid-State Circuits · 2010 · 52 citations

Low-power Electronics, Non-volatile Memory, Electrical Engineering +14

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection

Michael S. Floyd, P.J. Restle, Michael Sperling et al. · 2017 · 52 citations

Low-power Electronics, Power-aware Computing, Electrical Engineering +12

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

Eric Fluhr, Steve Baumgartner, D. Boerstler et al. · IEEE Journal of Solid-State Circuits · 2014 · 49 citations

Engineering, Core Throughput, Energy Efficiency +19

A DPLL-based per core variable frequency clock generator for an eight-core POWER7<sup>™</sup> microprocessor

José Tierno, Alexander Rylyakov, Daniel J. Friedman et al. · 2010 · 26 citations

Per-core Clock Generator, Engineering, Clock Recovery +13