José Tierno - Concepedia

Concepedia

Author

José Tierno

IBM Research - Thomas J. Watson Research Center

Also Known As

Herschel Ainspan, Jose A. Tierno, Jose Tierno, JosÉ A. Tierno, José A. Tierno, José Tierno, Tierno, Jose A., Tierno, José Andrés

27

Publications

1.3K

Citations

15

H-Index

44

Concepts

All Affiliations

IBM Research - Thomas J. Watson Research Center IBM (United States)University of Minnesota IBM Research - Austin Carnegie Mellon University

JT

About

José Tierno is an author at IBM Research - Thomas J. Watson Research Center specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	14	14	1.2K
2	Computer Engineering	14	14	1.2K
3	Computer Science	3	3	434
4	Education	1	1	50
5	Social Sciences	1	1	343

José Tierno

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15

Publications

1.3K

Citations

15

H-Index

	Year	Citations
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons Jae-sun Seo, Bernard Brezzo, Yong Liu, EngineeringComputer ArchitectureLimited ScalabilityNeurochipSocial Sciences	2011	343
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI José Tierno, Alexander Rylyakov, Daniel J. Friedman IEEE Journal of Solid-State Circuits Wide Tuning RangeElectrical EngineeringAdpll Lock RangeEngineeringVlsi Design	2008	193
Active management of timing guardband to save energy in POWER7 Charles Lefurgy, Alan J. Drake, Michael S. Floyd, EngineeringEnergy EfficiencyPower Optimization (Eda)Computer ArchitectureEnergy Management System	2011	138
Introducing the Adaptive Energy Management Features of the Power7 Chip Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, IEEE Micro EngineeringEnergy EfficiencyPower Optimization (Eda)Computer ArchitecturePower Electronics	2011	116
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignComputer ArchitectureBoth 4-Tap FfeIntegrated Circuits	2012	77
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing Bodhisatwa Sadhu, Mark Ferriss, Arun Natarajan, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignTransconductance Linearization	2013	72
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation Sameh Asaad, R. Bellofatto, Bernard Brezzo, EngineeringHardware Verification LanguageDesign PartitioningComputer ArchitectureHardware Security	2012	71
Active Guardband Management in Power7+ to Save Energy and Maintain Reliability Charles Lefurgy, Alan J. Drake, Michael S. Floyd, IEEE Micro EngineeringPower Optimization (Eda)Computer ArchitectureEnergy Management SystemHardware Security	2013	63
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL Mark Ferriss, Jean‐Olivier Plouchart, Arun Natarajan, IEEE Journal of Solid-State Circuits EngineeringRadio FrequencyMeasurementAnalog DesignEducation	2013	50
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology Timothy O. Dickson, Yong Liu, S.V. Rylov, IEEE Journal of Solid-State Circuits	2015	28

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