José Tierno

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

Jae-sun Seo, Bernard Brezzo, Yong Liu et al. · 2011 · 343 citations

Engineering, Computer Architecture, Limited Scalability +17

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI

José Tierno, Alexander Rylyakov, Daniel J. Friedman · IEEE Journal of Solid-State Circuits · 2008 · 193 citations

Wide Tuning Range, Electrical Engineering, Adpll Lock Range +12

Active management of timing guardband to save energy in POWER7

Charles Lefurgy, Alan J. Drake, Michael S. Floyd et al. · 2011 · 138 citations

Engineering, Energy Efficiency, Power Optimization (Eda) +16

Introducing the Adaptive Energy Management Features of the Power7 Chip

Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani et al. · IEEE Micro · 2011 · 116 citations

Engineering, Energy Efficiency, Power Optimization (Eda) +16

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson et al. · IEEE Journal of Solid-State Circuits · 2012 · 77 citations

Engineering, Vlsi Design, Computer Architecture +16