A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

TLDR

Scalable silicon implementations of spiking neural networks are hindered by limited analog neuron scalability, large learning circuit area that grows with synapses, and reliance on off‑chip address‑event communication. This work proposes a new architecture that combines robust digital neurons, transposable SRAM arrays sharing learning circuits that scale with neurons, and crossbar fan‑out for efficient on‑chip communication. The architecture tightly integrates memory and computation, yielding a 256‑neuron, 64K binary‑synapse chip with on‑chip spike‑timing‑dependent plasticity implemented in 45 nm SOI‑CMOS. The chip operates near‑threshold at 0.53 V, achieving power‑efficient real‑time pattern classification, recognition, and associative memory, and the architecture paves the way for ubiquitous ultra‑dense, ultra‑low‑power brain‑like cognitive computers.

Abstract

Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of analog neuron circuits; (b) the enormous area overhead of learning circuits, which grows with the number of synapses; and (c) the need to implement all inter-neuron communication via off-chip address-events. In this work, a new architecture is proposed to overcome these challenges by combining innovations in computation, memory, and communication, respectively, to leverage (a) robust digital neuron circuits; (b) novel transposable SRAM arrays that share learning circuits, which grow only with the number of neurons; and (c) crossbar fan-out for efficient on-chip inter-neuron communication. Through tight integration of memory (synapses) and computation (neurons), a highly configurable chip comprising 256 neurons and 64K binary synapses with on-chip learning based on spike-timing dependent plasticity is demonstrated in 45nm SOI-CMOS. Near-threshold, event-driven operation at 0.53V is demonstrated to maximize power efficiency for real-time pattern classification, recognition, and associative memory tasks. Future scalable systems built from the foundation provided by this work will open up possibilities for ubiquitous ultra-dense, ultra-low power brain-like cognitive computers.