Practical Strategies for Power-Efficient Computing Technologies

TLDR

Power dissipation limits silicon scaling, and achieving higher efficiency requires coordinated voltage scaling across devices, circuits, and systems, with radical changes in technology and architecture likely needed. The study identifies key issues for enhancing power efficiency under performance and area constraints and outlines promising radical methods for future reductions. The authors discuss solutions for logic devices, cache memory, interconnects, and power delivery, illustrating the approach with the IBM Blue Gene system as a case study. Focusing on an intermediate power‑performance range yields an approximately 8× improvement in power efficiency without sacrificing performance in parallelizable applications.

Abstract

After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an ~ 8× improvement in power efficiency can be attained without system performance loss in parallelizable applications-those in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.