Concepedia

Introducing the Adaptive Energy Management Features of the Power7 Chip

Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, José Tierno, Pradip Bose,

IEEE Micro · 2011 · 118 citations · 13 references

Abstract

Power7 implements several new adaptive power management techniques which, in concert with the EnergyScale firmware, let it proactively exploit variations in workload, environmental conditions, and overall system use to meet customer-directed power and performance goals. These innovative features include per-core frequency scaling with available autonomic frequency control, per-chip automated voltage slewing, power consumption estimation, and hardware instrumentation assist.

References

13

Runtime power monitoring in high-end processors: methodology and empirical data

Canturk Isci, Margaret Martonosi · 2003 · 497 citations

Engineering, Computer Engineering, Computer Science +15

Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

G. Semeraro, Grigorios Magklis, Rajeev Balasubramonian et al. · 2004 · 370 citations

Engineering, Computer Engineering, Computer Science +17

Runtime power monitoring in high-end processors: methodology and empirical data

Canturk Isci, Margaret Martonosi · 2004 · 289 citations

Engineering, Computer Engineering, Computer Science +15

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor

Alan J. Drake, Robert M. Senger, H.S. Deogun et al. · 2007 · 238 citations

Engineering, Computer Engineering, Electrical Engineering +14

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI

José Tierno, Alexander Rylyakov, Daniel J. Friedman · IEEE Journal of Solid-State Circuits · 2008 · 194 citations

Engineering, Electrical Engineering, Analog Electronics +16