Rajeev Balasubramonian

Author

University of Utah ORCID

Also Known As

R. Balasubramonian, Rajeev Balasubramonian, Vivek Srikumar

146

Publications

9.3K

Citations

H-Index

112

Concepts

All Affiliations

University of Utah Hewlett-Packard (United States)University of Rochester Intel (United States)The University of Texas at Austin

About

Rajeev Balasubramonian is an author at University of Utah specializing in computer architecture, computer engineering, and parallel computing.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	41	66	7.6K
2	Management	3	3	413
3	Social Sciences	2	2	134
4	Arts	1	1	10
5	Natural Sciences	1	1	28

Rajeev Balasubramonian

Publications

Citations

H-Index

Page 1

	Year	Citations
ISAAC Ali Shafiee, Anirban Nag, Naveen Muralimanohar, ACM SIGARCH Computer Architecture News EngineeringHardware AccelerationData ScienceHardware AlgorithmComputer Architecture	2016	1.5K
CACTI 6.0: A Tool to Model Large Caches Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi	2009	850
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars Ali Shafiee, Anirban Nag, Naveen Muralimanohar, EngineeringHardware AccelerationData ScienceHardware AlgorithmComputer Architecture	2016	673
CACTI 7 Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, ACM Transactions on Architecture and Code Optimization Non-volatile MemoryMemory ArchitectureEngineeringMemory DesignHigh-performance Architecture	2017	474
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu,	2000	366
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling G. Semeraro, Grigorios Magklis, Rajeev Balasubramonian, Energy-efficient Processor DesignEngineeringVlsi DesignEnergy EfficiencyPower Optimization (Eda)	2004	364
Overcoming the challenges of crossbar resistive memory architectures Cong Xu, Dimin Niu, Naveen Muralimanohar, Write LatencyElectrical EngineeringNon-volatile MemoryEngineeringEmerging Memory Technology	2015	325
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads Seth H. Pugsley, Jeffrey Jestes, Huihui Zhang, Cluster ComputingEngineeringNdc DesignComputer ArchitectureMap-reduce	2014	249
Rethinking DRAM design and organization for energy-constrained multi-cores Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, EngineeringComputer ArchitectureMulti-channel Memory ArchitectureHardware SecurityDram Vendors	2010	237
Near-Data Processing: Insights from a MICRO-46 Workshop Rajeev Balasubramonian, Jichuan Chang, Troy D. Manning, IEEE Micro Cluster ComputingEngineeringCareful ExaminationBig Data InfrastructureNear-data Processing	2014	234

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