Alper Buyuktosunoglu

Author

IBM (United States)ORCID

Also Known As

A. Buyuktosunoglu, Alper Buyuktosunoglu, Buyuktosunoglu, Alper

173

Publications

5.2K

Citations

H-Index

131

Concepts

All Affiliations

IBM (United States)IBM Research - Thomas J. Watson Research Center Universitat Politècnica de Catalunya University of Rochester Barcelona Supercomputing Center

About

Alper Buyuktosunoglu is an author at IBM (United States) specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	31	66	4.1K
2	Computer Engineering	31	64	4.1K
3	Management	1	1	29
4	Social Sciences	1	1	12
5	Cognitive Science	1	1	12

Alper Buyuktosunoglu

Publications

4.8K

Citations

H-Index

Page 1

	Year	Citations
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget Canturk Isci, Alper Buyuktosunoglu, C.-Y. Chen, Proceedings of the ... annual International Symposium on Microarchitecture/Proceedings of the annual International Symposium on Microarchitecture Distributed Energy SystemEngineeringEnergy EfficiencyPower Optimization (Eda)Computer Architecture	2006	620
Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors Peter W. Cook, Manoj Gupta, Victor Zyuban, IEEE Micro Hardware SecurityEarly DesignPower-aware ComputingElectrical EngineeringEngineering	2000	504
Microarchitectural techniques for power gating of execution units Zhigang Hu, Alper Buyuktosunoglu, V. Srinivasan, Hardware SecurityArchitectural TechniquesPower-aware ComputingEngineeringProgram Analysis	2004	388
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu,	2000	366
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads Seth H. Pugsley, Jeffrey Jestes, Huihui Zhang, Cluster ComputingEngineeringNdc DesignComputer ArchitectureMap-reduce	2014	249
Dynamically tuning processor resources with adaptive processing David H. Albonesi, Rajeev Balasubramonian, S.G. Dropsbo, Computer Processor ResourcesEngineeringDecision LogicComputer ArchitectureSoftware Engineering	2003	156
Integrating adaptive on-chip storage structures for reduced dynamic power S. Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, International Conference on Parallel Architectures and Compilation Techniques Reduced Dynamic PowerStorage PerformanceEngineeringEnergy EfficiencyComputer Architecture	2002	118
Introducing the Adaptive Energy Management Features of the Power7 Chip Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, IEEE Micro EngineeringEnergy EfficiencyPower Optimization (Eda)Computer ArchitecturePower Electronics	2011	116
A circuit level implementation of an adaptive issue queue for power-aware microprocessors Alper Buyuktosunoglu, David H. Albonesi, S.E. Schuster, EngineeringComputer ArchitectureClaims GlsvlsiAdaptive Issue QueueHigh Performance Computing	2001	91
Long-Term Workload Phases: Duration Predictions and Applications to DVFS Canturk Isci, Alper Buyuktosunoglu, Margaret Martonosi IEEE Micro EngineeringComputer ArchitectureWorkload BehaviorLong-term Workload PhasesPerformance Issue	2005	86

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