Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors

Abstract

The ability to estimate power consumption during early-stage definition and trade-off studies is a key new methodology enhancement. Opportunities for saving power can be exposed via microarchitecture-level modeling, particularly through clock-gating and dynamic adaptation. In this paper we describe the approach of using energy-enabled performance simulators in early design. We examine some of the emerging paradigms in processor design and comment on their inherent power-performance characteristics.