Microarchitectural techniques for power gating of execution units

TLDR

Leakage power is a major concern in current and future microprocessor designs. The study investigates architectural techniques to reduce leakage by power‑gating execution units. The authors derive analytical break‑even equations and evaluate floating‑point and fixed‑point units in a state‑of‑the‑art out‑of‑order superscalar model using ideal, time‑based, and branch‑misprediction‑guided sleep‑mode detection techniques. The experiments show that time‑based power‑gating lets floating‑point units sleep up to 28% of cycles with only a 2% performance loss, while branch‑misprediction‑guided gating enables fixed‑point units to sleep 40% more cycles than the time‑based method with comparable performance impact, demonstrating the effectiveness of architectural power‑gating.

Abstract

Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical equations that estimate the break-even point for application of power-gating techniques. The potential for power gating execution units is then evaluated, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-of-order superscalar processor model. The power gating potential of the floating-point and fixed-point units of this processor is then evaluated using three different techniques to detect opportunities for entering sleep mode; ideal, time-based, and branch-misprediction-guided. Our results show that using the time-based approach, floating-point units can be put to sleep for up to 28% of the execution cycles at a performance loss of 2%. For the more difficult to power-gate fixed-point units, the branch misprediction guided technique allows the fixed-point units to be put to sleep for up to 40% more of the execution cycles compared to the simpler time-based technique, with similar performance impact. Overall, our experiments demonstrate that architectural techniques can be used effectively in power-gating execution units.