Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling

TLDR

As clock frequency increases and feature size decreases, clock distribution and wire delays pose a growing challenge to designers of singly‑clocked, globally synchronous systems. We propose a multiple clock domain (MCD) processor that partitions the chip into several domains, each capable of independent voltage and frequency scaling. The design divides the chip into four domains—front end, integer, floating point, and load‑store—using queue boundaries to minimize inter‑domain synchronization, and is evaluated with SimpleScalar/Wattch simulations and off‑line trace analysis to identify profitable reconfiguration points for dynamic scaling. Using MediaBench, Olden, and SPEC2000 benchmarks, the MCD approach achieves an average 20 % improvement in energy‑delay product versus a 3 % gain from voltage scaling a single clock system.

Abstract

As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. We describe an alternative approach, which we call a multiple clock domain (MCD) processor, in which the chip is divided into several clock domains, within which independent voltage and frequency scaling can be performed. Boundaries between domains are chosen to exploit existing queues, thereby minimizing inter-domain synchronization costs. We propose four clock domains, corresponding to the front end , integer units, floating point units, and load-store units. We evaluate this design using a simulation infrastructure based on SimpleScalar and Wattch. In an attempt to quantify potential energy savings independent of any particular on-line control strategy, we use off-line analysis of traces from a single-speed run of each of our benchmark applications to identify profitable reconfiguration points for a subsequent dynamic scaling run. Using applications from the MediaBench, Olden, and SPEC2000 benchmark suites, we obtain an average energy-delay product improvement of 20% with MCD compared to a modest 3% savings from voltage scaling a single clock and voltage system.