G. Semeraro - Concepedia

Concepedia

Author

G. Semeraro

University of Rochester

Also Known As

G. Semeraro, Greg Semeraro

15

Publications

1.1K

Citations

11

H-Index

30

Concepts

All Affiliations

University of Rochester Rochester Institute of Technology

GS

About

G. Semeraro is an author at University of Rochester specializing in parallel computing, engineering, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	10	10	990
2	Computer Engineering	10	10	990
3	Computer Science	8	8	811
4	Electrical Engineering	7	7	777
5	Systems Engineering	4	4	608

G. Semeraro

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11

Publications

1.1K

Citations

11

H-Index

	Year	Citations
Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling G. Semeraro, Grigorios Magklis, Rajeev Balasubramonian, Energy-efficient Processor DesignEngineeringVlsi DesignEnergy EfficiencyPower Optimization (Eda)	2004	364
Dynamically tuning processor resources with adaptive processing David H. Albonesi, Rajeev Balasubramonian, S.G. Dropsbo, Computer Processor ResourcesEngineeringDecision LogicComputer ArchitectureSoftware Engineering	2003	156
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor Grigorios Magklis, Michael L. Scott, G. Semeraro,	2003	148
Integrating adaptive on-chip storage structures for reduced dynamic power S. Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, International Conference on Parallel Architectures and Compilation Techniques Reduced Dynamic PowerStorage PerformanceEngineeringEnergy EfficiencyComputer Architecture	2002	118
Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor Grigorios Magklis, G. Semeraro, David H. Albonesi, IEEE Micro EngineeringVlsi DesignComputer ArchitectureMultiple Clock DomainsMultiple Clock Domain	2003	104
Dynamic frequency and voltage control for a multiple clock domain microarchitecture G. Semeraro, David H. Albonesi, S. Dropsho, Mcd MicroarchitectureEngineeringVlsi DesignEnergy EfficiencyVoltage Control	2003	75
Integrating adaptive on-chip storage structures for reduced dynamic power S. Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, Reduced Dynamic PowerStorage PerformanceEngineeringEnergy EfficiencyComputer Architecture	2003	51
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor Grigorios Magklis, Michael L. Scott, G. Semeraro, ACM SIGARCH Computer Architecture News EngineeringVlsi DesignEnergy EfficiencyComputer ArchitectureMcd Processor	2003	33
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor Grigorios Magklis, Michael L. Scott, G. Semeraro, EngineeringVlsi DesignEnergy EfficiencyComputer ArchitectureMcd Processor	2003	32
Hiding synchronization delays in a GALS processor microarchitecture G. Semeraro, David H. Albonesi, Grigorios Magklis, EngineeringSynchronization ProtocolSynchronization DelaysAlpha 21264-Like ProcessorHigh-performance Architecture	2004	31

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