Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor

TLDR

Multiple clock domains address the challenge of propagating clock signals across large, fast chips and enable independent frequency and voltage scaling to reduce power dissipation. The MCD microarchitecture employs a globally asynchronous, locally synchronous (GALS) style, keeping each domain internally synchronous while allowing independent voltage and frequency control for dynamic scaling.

Abstract

Multiple clock domains is one solution to the increasing problem of propagating the clock signal across increasingly larger and faster chips. The ability to independently scale frequency and voltage in each domain creates a powerful means of reducing power dissipation. A multiple clock domain (MCD) microarchitecture, which uses a globally asynchronous, locally synchronous (GALS) clocking style, permits future aggressive frequency increases, maintains a synchronous design methodology, and exploits the trend of making functional blocks more autonomous. In MCD, each processor domain is internally synchronous, but domains operate asynchronously with respect to one another. Designers still apply existing synchronous design techniques to each domain, but global clock skew is no longer a constraint. Moreover, domains can have independent voltage and frequency control, enabling dynamic voltage scaling at the domain level.