A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor

Abstract

A distributed critical-path timing monitor (CPM) is designed as part of the POWER6trade microprocessor in 65nm SOI. The CPM is capable of monitoring timing margin, process variation, localized noise and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> droop, or clock stability. It tracks critical-path delay to within 3 FO2 delays at extreme operating voltages with a standard deviation less than frac12 an FO2 delay. The CPM detects DC V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> droops greater than 10mV and tracks timing changes greater than 1 FO2 delay.