A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

Abstract

This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the equalization system self-contained in the receiver. This design extends existing power-efficient DFEs based on current-integrating summers and adds FFE functionality to the DFE circuit infrastructure for an efficient implementation. Key techniques for implementing receive-side FFE are: the use of multiphase quarter-rate sample-and-hold circuits for generating multiple time-shifted input data signals, time-based analog multiplication for FFE coefficient weighting, and a merged FFE/DFE summer. The receiver test chip, implemented in a 45-nm silicon-on-insulator (SOI) CMOS technology, occupies 0.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and has a power efficiency of 6.2 mW/Gb/s at 19 Gb/s. Step-reponse characterization of the receiver demonstrates accurate FFE computation. The receiver equalizes a 35-in PCB trace at 17 Gb/s with a channel loss of 30 dB at 8.5 GHz and a 20-in PCB trace at 19 Gb/s with a channel loss of 25 dB at 9.5 GHz.