A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization

T. Beukema, M. Sorna, K. Selander, +8

IEEE Journal of Solid-State Circuits

System On ChipLow JitterVlsi DesignEngineeringAnalog-to-digital Converter +12

40-Gb/s circuits built from a 120-GHz f/sub T/ SiGe technology

G. Freeman, Mounir Meghelli, Young Kwark, +10

IEEE Journal of Solid-State Circuits

40-Gb/s CircuitsElectrical EngineeringEngineeringVlsi DesignHigh-frequency Device +9

A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems

Mounir Meghelli, Alexander Rylyakov, S. Zier, +2

IEEE Journal of Solid-State Circuits

43-Gb/s ReceiverElectrical EngineeringEngineeringVlsi DesignHigh-speed Electronics +11

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, +14

IEEE Journal of Solid-State Circuits

Electrical EngineeringEngineeringVlsi DesignVoltage OffsetMulti-standard Backplane Applications +10

A 6.4Gb/s CMOS SerDes core with feedforward and decision-feedback equalization

M. Sorna, T. Beukema, K. Selander, +7

System On Chip4-Tap FfeEngineeringVlsi DesignCircuit System +10

0.13 μm 210 GHz f/sub T/ SiGe HBTs - expanding the horizons of SiGe BiCMOS

Alvin Joseph, Douglas Coolbaugh, D.L. Harame, +13

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

10+ gb/s 90-nm CMOS serial link demo in CBGA package

S.V. Rylov, Scott Reynolds, D. Storaska, +5

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringCbga PackageVlsi DesignEngineering +11

SiGe BiCMOS integrated circuits for high-speed serial communication links

Daniel J. Friedman, Mounir Meghelli, B. Parker, +9

IBM Journal of Research and Development

Electrical EngineeringEngineeringVlsi DesignHigh-speed ElectronicsCircuit Design +11

A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology

Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, +14

Electrical EngineeringEngineeringVlsi DesignVoltage OffsetMulti-standard Backplane Applications +10

Multi Gbit/s, high-sensitivity all silicon 3.3 V optical receiver using PIN lateral trench photodetector

J.D. Schaub, D.M. Kuchta, D.L. Rogers, +4

Free-space Optical NetworkPhotonicsImage SensorEngineeringOptical Transmission System +13